Updated Memory Wall (markdown) authored by moebiusband73's avatar moebiusband73
...@@ -43,9 +43,10 @@ bandwidth develop in parallel over the years. What about all the cores added? ...@@ -43,9 +43,10 @@ bandwidth develop in parallel over the years. What about all the cores added?
And there we are at a new wall processor architecture is facing: The power And there we are at a new wall processor architecture is facing: The power
wall. Processors are sophisticated heating plates, the performance limit is wall. Processors are sophisticated heating plates, the performance limit is
governed by the total heat you can dissipate across the tiny die surface. Due governed by the total heat you can dissipate across the tiny die surface. Due
to this limitation hardware architects trade cores for frequency, from 3.6 GHz to this limitation hardware architects trade used cores for frequency, from 3.6 GHz
in Pentium D to 2 GHz nowadays. To achieve a performance in Pentium D to 2 GHz nowadays. You have to give engineers credit for dynamically giving you a higher frequency if not using all cores.
increase the engineers silently increased the TDP (Thermal design power) from A feature called Turbo mode.
To achieve a performance increase the engineers silently increased the TDP (Thermal design power) from
96W in Nehalem to 205W in Cascadelake. Despite these efforts the performance levels off lately compared to 96W in Nehalem to 205W in Cascadelake. Despite these efforts the performance levels off lately compared to
the single core era where performance was mainly driven by huge frequency increases. the single core era where performance was mainly driven by huge frequency increases.
The memory bandwidth was also significantly increased over the years by adding more memory channels, but also by increasing the memory clock. With standard DRAM technology you The memory bandwidth was also significantly increased over the years by adding more memory channels, but also by increasing the memory clock. With standard DRAM technology you
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